Temperature compensated monolithic delay circuit

ABSTRACT

A temperature and processing compensated time delay circuit of the type which can be fabricated in a monolithic integrated circuit utilizes a field effect transistor (FET) (12) connected to the terminals of a charged capacitor (14). A bias voltage connected to the gate of the FET (12) varies with temperature in a manner to compensate for the changes in current which flows from the capacitor (14) through the FET (12) due to changes in temperature. The bias voltage also varies from one integrated circuit to another in a manner to compensate for variations in FET threshold voltage caused by variations in the processing of the integrated circuits.

This is a continuation application Ser. No. 217,142, filed 6/30/88.

TECHNICAL FIELD

This invention relates to delay circuits and more particularly to delaycircuits fabricated in monolithic integrated circuits.

BACKGROUND OF THE INVENTION

Delay circuits are used in various electronic circuits for functionssuch as matching timing delays inside integrated circuits to avoid raceconditions, and for device independent time delays. The circuits forgenerating the device independent time delays are generally eitherhybrid delay lines which use small discrete L and C elements, ormonostable multivibrator integrated circuits or "one shots".

The device independent time delay circuits are designed to beessentially insensitive to variations in ambient temperature, on theorder of 1000 parts per million (PPM) per degree Centigrade and invariations of supply voltage. The term "essentially", as used herein,means closely approximating to a degree sufficient for practicalpurposes.

At present, because of the relative complexity of one shots, the onlyviable form of device independent delay circuits for providing aplurality of delayed signals from one input signal is the hybrid delayline. However, the hybrid delay lines tend to be expensive tomanufacture compared to most integrated circuits, and tend not to be asreliable as monolithic I.C.'s.

It can therefore be appreciated that an independent time delay circuitwhich is able to provide a plurality of time delays from a single inputsignal and which can be fabricated using standard integrated circuitfabrication techniques is highly desirable.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide a delaycircuit which can be fabricated in a monolithic integrated circuit,which is small enough to be repeated several times in such circuit andwhich is essentially insensitive to changes in temperature.

As shown in an illustrated embodiment of the invention, a chargedcapacitor is connected to discharge through a field effect transistor(FET) having a bias voltage applied to the gate terminal thereof. Thebias voltage varies with temperature in a manner to effectivelycompensate for temperature variations in the FET.

A further aspect of the illustrated invention is a circuit forgenerating a bias voltage for a FET which effectively compensates fortemperature variations in the FET and which effectively compensates fordiffering transistor characteristics from one integrated circuit toanother.

Still another aspect of the present invention is a method for generatingan essentially temperature stable delay circuit by charging a capacitorto a first voltage and discharging the capacitor through a FET. Thetemperature stability occurs by compensating for the temperaturevariations in the FET by generating inverse variations in the FET gatebias voltage.

BRIEF DESCRIPTION OF THE DRAWINGS

The aforementioned and other features, characteristics, advantages, andthe invention in general, will be better understood from the followingmore detailed description taken in conjunction with the accompanyingdrawings in which:

FIG. 1a is a schematic diagram of the basic delay circuit according tothe present invention;

FIG. 1b is a plot of the voltage across the capacitor during operationof the circuit of FIG. 1a;

FIG. 1c is a preferred embodiment of the present invention of theschematic diagram of FIG. 1a;

FIG. 2a is a schematic diagram of a delay circuit including a biasvoltage circuit and a comparator circuit according to the presentinvention; and

FIG. 2b is a plot of the input voltage versus the output voltage for thecircuit of FIG. 2a.

It will be appreciated that, where considered appropriate, referencenumerals have been repeated in both figures to indicate correspondingfeatures.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention provides a delay circuit in which a chargedcapacitor is discharged through a field effect transistor (FET). A biasvoltage applied to the gate of the FET varies with temperature in amanner to effectively compensate for temperature variations in the FET.

Turning now to the drawings, FIG. 1a shows a schematic diagram for thebasic timing circuit according to the present invention shown generallyas element 10. A field effect transistor designated herein as FET 12 hasits source terminal thereof connected to one terminal of a capacitor 14and its drain terminal connected to a switch 16. The FET 12 is ann-channel enhancement-mode transistor having a threshold voltage tobecome conductive of typically 0.7 volts. The other side of the switch16 is connected to the other terminal of the capacitor 14. The gateterminal of the transistor 12 is connected to a bias voltage V_(BIAS) ata node 18.

The operation of the circuit of FIG. 1a will now be described withrespect to FIG. 1b. Before time t=0 the capacitor 14 is charged to afirst voltage shown as V_(CHARGED) in FIG. 1a. At time t=0 switch 16closes, completing the circuit through the FET 12. The bias voltageV_(BIAS) is such that the FET 12 operates in its saturation region andtherefore operates essentially as a constant current drain to thecapacitor 14. Since the current from the capacitor 14 is constant, thevoltage across the capacitor 14 decreases at essentially a constant rateas shown in FIG. 1b. A voltage detector not shown in FIG. 1a monitorsthe voltage across the capacitor 14 and provides an output signal whenthe voltage reaches a trip voltage shown as V_(TRIP) in FIG. 1b. Thedifference between V_(CHARGED) and V_(TRIP) is shown as V_(DELTA) inFIG. 1b.

In order for the circuit of FIG. 1a to have a time delay which isindependent of temperature, the voltage V_(DELTA) must be independent oftemperature. This implies that the current through the FET 12 must alsobe independent of temperature. However, it is well known that thecurrent through an FET is not constant with temperature, but, instead,varies with temperature. In the present invention, compensation for thetemperature variations in the FET is achieved by circuitry whichprovides appropriate changes in the gate-to-source voltage applied tothe FET.

The basic (somewhat simplified) formula for current flowing through anFET biased to operate in the saturation region is

    I=u(C.sub.ox /2)(W/L)(V.sub.gate -V.sub.th).sup.2          (1)

where u is the surface mobility, C_(ox) is the capacitance per unit areaof the gate oxide, W is the width of the FET channel region, L is thelength of the FET channel region, V_(gate) is the gate-to-source voltageand V_(th) is the threshold voltage of the FET. If the gate-to-sourcevoltage is set to be equal to a reference voltage plus a thresholdvoltage (V_(ref) +V_(th)) then equation (1) becomes

    I=u(C.sub.ox /2)(W/L)(V.sub.ref).sup.2                     (2)

For the capacitor 14 of FIG. 1a, the time T for the capacitor 14 todischarge a voltage V_(DELTA) is given by the formula

    T=(CV.sub.DELTA)/I                                         (3)

where C is the capacitance of the capacitor and I is the current flowingfrom the capacitor. For a capacitor formed in a monolithic integratedcircuit, the capacitance is given by

    C=C.sub.ox A                                               (4)

where C_(ox) is the capacitance per unit area of the oxide layer and Ais the area of the capacitor. Combining equations (2), (3) and (4)together provides

    T=(2AV.sub.DELTA)/((W/L)uV.sub.ref.sup.2).                 (5)

An examination of equation (5) reveals that all of the terms are, or canbe made, temperature independent except for u, the surface mobilityterm. The present invention compensates for the variations in u byproviding compensating variations in the term V_(ref) in equation (5).

It has been found, for the wafer processing used to manufactureintegrated circuits of the type used to embody the present invention,and for a first order approximation, that u decreases linearly as thetemperature increases. Accordingly if u has a relative value of 1.000 atzero degrees Centigrade, then it will have a relative value of 0.832 at55 degrees Centigrade (273/328), and a relative value of 0.773 at 80degrees Centigrade (273/353). If the term u V_(ref) is made to beindependent of temperature, then equation (5) can be made to beindependent of temperature. In other words, if the value of u at 55degrees relative to the value of u at zero degrees times the value ofV_(ref) ² at 55 degrees relative to the value of V_(ref) ² at zerodegrees is equal to one, and similarly for 80 degrees Centigrade, thenthe time delay T will be independent of temperature to a first orderapproximation. Therefore, the relative value of V_(ref) at 55 degreesCentigrade must be equal to the square root of the inverse of 0.832 or1.096. Similarly, the relative value of V_(ref) at 80 degrees must be1.137.

From the above it is evident that V_(ref) must increase with temperaturein a nonlinear manner. It was found that an equation of the form V₁ -K₂V_(be) will provide a fairly accurate fit to the above requirements ifthe parameters V₁ and K₂ are chosen properly. The term V₁ represents areference voltage that is essentially independent of power supplyvoltage variations and of temperature variations, and V_(be) representsthe normal base-emitter voltage drop of a bipolar transistor operatingin its active region (i.e., not in cutoff or saturation). In thepreferred embodiment the value of V₁ was selected as 3.775 volts, andthe value of K₂ was selected as 3.

The circuit shown in FIG. 1a is, in the present invention, preferablyembodied by a similar circuit shown in FIG. 1c. As shown in FIG. 1c thetwo terminals of the capacitor 14 and the source and drain of the FET 12are connected in parallel, respectively, without a switch between them.The source of the FET 12 is connected to V_(SS). Connected to the drainof FET 12 is a resistor R_(SMALL), the other side of which is connectedto one terminal of a switch 19, while the other terminal of the switch19 is connected to V_(CC). V_(CC) is the normal supply voltage to theintegrated circuit that embodies the present invention and typically isat 5 volts. In operation the FET 12 is made always conductive by thebias voltage V_(BIAS). When the switch 19 is closed, the capacitor 14 ischarged to approximately V_(CC) through R_(SMALL). Although the FET 12is also conductive at this time, the drain-to-source resistance of theFET 12 is much greater than the resistance of R_(SMALL). When the switch19 is open, then the voltage on the capacitor is discharged through theFET 12 as described above. For an alternate embodiment, a tighter delaytolerance can advantageously be obtained by connecting the switch 19 toa regulated power supply node that has a tighter voltage tolerance thanis generally conventional for the normal supply voltage V_(CC).

Turning now to FIG. 2a, the timing circuit including the bias voltagegenerating circuitry according to the present invention is showngenerally as element 20. Included in FIG. 2a is FET 12 and capacitor 14of the basic timing circuit of FIG. 1a. The source of FET 12 and firstterminal of the capacitor 14 is connected to a reference voltage shownin FIG. 2a as V_(SS). The drain of the FET 12 and the second terminal ofthe capacitor 14 are connected to the drain of a p-channelenhancement-mode pullup FET 22, the gate of which is connected to aninput voltage V_(IN) at input terminal 24, and the source of the FET 22is connected to V_(CC). Also connected to the drain of the FET 12 is thepositive input of a voltage comparator 26, the negative input terminalof which is connected to a voltage V_(TRIP). V_(TRIP) is selected to bea voltage equal to approximately one-half that of V_(CC). The output ofthe comparator 26 provides an output voltage shown as V_(OUT).

The operation of the circuit shown in FIG. 2a described so far will bedescribed with reference to FIG. 2b. As shown in FIG. 2b, when the inputvoltage V_(IN) is at a logical low voltage level, FET 22 is sufficientlyconductive to force the voltage on capacitor 14 to be essentially atV_(CC). (It will be assumed throughout this discussion that V_(SS) is atground potential relative to the other voltages in the circuit.) It willbe appreciated by those skilled in the art that while the FET 12 is alsoconductive at this time, the relative size ratio between the FET 12 andthe FET 22 is such that the FET 22 can supply much more current than theFET 12 can sink. Since the voltage across the capacitor 14 is greaterthan the voltage at the negative input to the comparator 26, the outputof the comparator 26, V_(OUT), is at a logical high voltage level. Attime t=0 the input voltage changes from a logical low voltage level to alogical high voltage level, causing the FET 22 to become nonconducting.At this time the voltage on the capacitor 14 begins to discharge throughthe FET 12 in the manner described above in reference to FIG. 1a andFIG. 1b. The output of the comparator 26 will remain at a logical highvoltage level until the voltage across the capacitor 14 is slightly lessthan the voltage at the negative input terminal of the comparator 26.When the voltage across the capacitor 14 becomes slightly less than thistrip voltage, the output of the comparator 26 will change to a logicallow voltage level. In this manner a positive transition in the inputvoltage is delayed. Later when the input voltage returns to a logicallow voltage level, the FET 22 immediately becomes conductive and,because the FET 22 is able to supply a relatively large amount ofcurrent to the capacitor 14, quickly charges the capacitor 14 almost toV_(CC). This in turn changes the state of the output voltage V_(out) ofthe comparator 26. Thus, a negative transition in the input voltage istransferred to the output with only a small, generally negligible,delay.

Turning now to the circuitry for generating the bias voltage driving thegate of the FET 12 in FIG. 2a, a noninverting amplifier 32 has itspositive or noninverting input connected to a voltage V_(BG), itsnegative or inverting input connected to the common connection of afeedback resistor 34 and an input resistor 36. The other end of theinput resistor 36 is connected to V_(SS), and the other end of thefeedback resistor 34 in connected to the output of the amplifier 32.V_(BG) is derived from a band-gap voltage generating circuit not shownin FIG. 2a. Band-gap circuits, which are well known in the art, producea voltage which is stable over temperature. A first bipolar transistor38 has its base connected to the output of the amplifier 32, itscollector connected to V_(CC), and its emitter connected to the drain ofa first current source FET 40. A second bipolar transistor 42 has itsbase connected to the emitter of the transistor 38, its collectorconnected to V_(CC) and its emitter connected to the drain of a secondcurrent source FET 44. A third bipolar transistor 46 has its baseconnected to the emitter of transistor 42, its collector connected toV_(CC) and its emitter connected to the drain of a third current sourceFET 48. The sources of the FETs 40, 44 and 48 are connected together andto V_(SS). The gates of the FETs 40, 44 and 48 are connected togetherand to the common connection of the drains of two series FETs, ap-channel FET 50 and an n-channel FET 52. The source of the FET 50 isconnected to V_(CC) and the gate of the FET 50 is connected to V_(SS).The source of the FET 52 is connected to V_(SS) and the gate of the FET52 is connected to the common connection of the drains of the FETs 50and 52.

The emitter of the bipolar transistor 46 is connected to the source of athreshold offset FET 54. The drain of the FET 54 is connected to thegate of the FET 54 and to the drain of a current source FET 56. Thesource of the FET 56 is connected to V_(CC) and the gate of the FET 56is connected to a node formed by the connection of the source of a firstbias FET 58 and the drain of a second bias FET 60. The gate and drain ofthe first bias FET 58 are connected to V_(SS). The gate of the secondbias FET 60 is connected to the drain of the second bias FET 60, and thesource of the second bias FET 60 is connected to the drain and gate of athird bias FET 62, the source of which is connected to V_(CC). Thecurrent source FET 56 and the bias FETs 58, 60 and 62 are p-channelFETs. Except as stated otherwise all of the FETs shown in FIG. 2a aren-channel enhancement mode FETs. Connected to the gate and drain of thethreshold offset FET 54 is the positive or noninverting input of abuffer amplifier 64. The negative or inverting input of the bufferamplifier 64 is connected to the output of the buffer amplifier 64 andto the gate of the FET 12, thus completing the bias circuitry. Each ofthe elements of the bias circuitry is suitable for fabrication in aconventional CMOS integrated circuit.

The bias voltage circuitry just described produces a bias voltage equalto V₁ -K₂ V_(be) +V_(th). The V₁ term is generated by the amplifier 32together with resistors 34 and 36 and V_(BG). The band gap referencevoltage V_(BG) is typically at 2.5 volts and is used instead of V_(CC)because it is essentially independent of temperature and power supplyvariations. Thus the voltage out of the amplifier 32 is essentiallystable and independent of temperature and power supply variations. TheFETs 50 and 52 provide a bias voltage for the FETs 40, 44 and 48 whichin turn control the current through the bipolar transistors 38, 42 and46 respectively in order to keep the bipolar transistors operating intheir active region. The voltage at the emitter of transistor 38 is onebase-emitter voltage drop lower than the voltage at the output of theamplifier 32. Similarly, the voltage at the emitter of the transistor 46is three base-emitter voltage drops (3V_(be)) lower than the voltage atthe output of the amplifier 32. The current source FET 56 operates tosupply a relatively constant current through the threshold offset FET 54which is connected to operate in its saturation region. The bias FETs58, 60 and 62 provide the proper gate voltage to the current source FET56 to keep it conductive but at a low current level. The voltage at thegate of the threshold offset FET 54 will be one n-channel thresholdvoltage higher than the voltage at the source of the threshold offsetFET 54. Therefore, the voltage at the gate of the threshold offset FET54 is equal to V.sub. 1 -K₂ V_(be) +V_(th). Since the impedance at thegate of threshold offset FET 54 is high, the gate of FET 12 issusceptible to noise from other portions of the integrated circuit. Toalleviate this problem, the buffer amplifier 64 is configured to beunity gain and is used to provide a low impedance voltage source for thegate of the FET 12.

The V_(th) term generated by the bias voltage circuitry will vary fromone integrated circuit to another due to processing variations whichcause differing transistor characteristics. For a given integratedcircuit, however, the threshold voltage of the FET 54 will normally bevery close to that of the FET 12. Consequently, if the threshold voltageof the FET 12 is higher or lower than typical, the bias voltagecircuitry will generate a correspondingly higher or lower bias voltage,thereby maintaining a constant current through the FET 12 despitevariations in threshold voltage from one integrated circuit to another.Thus, the element 20 is self-compensating with respect to integratedcircuit processing variations. Similarly, the element 20 isself-compensating with respect to any changes in the threshold voltageof the FET 12 caused by temperature changes or by long-term drift.

Although the invention has been described in part by making detailedreference to a certain specific embodiment, such detail is intended tobe and will be understood to be instructive rather than restrictive. Itwill be appreciated by those skilled in the art that many variations maybe made in the structure and mode of operation without departing fromthe spirit and scope of the invention, as disclosed in the teachingscontained herein. For example the conductivity type of the FETs can bechanged by making appropriate changes to the supply voltage and gateconnections of some of the FETs as will be understood by those skilledin the art. Also the number of bipolar transistors used to create a likenumber of base-emitter voltage drops may be increased or decreased toprovide more or less temperature variation in the bias voltage on thegate of the FET 12. For another alternative, increased accuracy can beachieved by utilizing circuitry for generating V_(TRIP) that maintainsV_(DELTA) constant even though V_(CHARGED) might vary somewhat.

What is claimed is:
 1. A timing circuit, comprising:a capacitor; a firstfield-effect transistor, comprising a gate, connected to discharge saidcapacitor; an additional stage, connected to said capacitor andconfigured to change state when said capacitor is discharged to apredetermined voltage; a plurality of bipolar transistors, connected toreduce a temperature-independent reference voltage by a multiple of thebase-emitter voltage drop of one of said plurality of bipolartransistors, to provide a temperature-dependent reference potential; asecond field-effect transistor, having source and drain terminals conbetween a first current source and said temperature-dependent referencepotential having a gate connected to said drain terminal thereof; saidgate of said first field-effect transistor being coupled to said gate ofsaid second field-effect transistor so that said gate of said firstfield-effect transistor receives a voltage corresponding to the voltageon said gate of said second field-effect transistor.
 2. The circuit ofclaim 1 wherein said additional stage consists essentially of acomparator.
 3. The circuit of claim 1, wherein said gate of said firstfield-effect transistor is coupled to said gate of said secondfield-effect transistor through a buffer amplifier.
 4. The circuit ofclaim 1, wherein said gate of said first field-effect transistor iscoupled to the output of a buffer amplifier having unity gain and lowsource impedance, and the input of said buffer amplifier is connected tosaid gate of said second field-effect transistor.
 5. The circuit ofclaim 1, wherein said temperature-independent reference voltage isderived from a bandgap voltage reference.
 6. The circuit of claim 1,further comprising a switching transistor connected to rapidly chargesaid capacitor.
 7. The circuit of claim 1, further comprising aplurality of second current sources, each of said second current sourcesbeing connected to keep a respective one of said bipolar transistorsoperating in its active region.
 8. The circuit of claim 1, wherein afirst one of said plurality of bipolar transistors comprises a base,connected to said temperature-independent reference voltage, and anemitter; and a second one of said plurality of bipolar transistorscomprises a base, connected to said emitter of said first bipolartransistor.
 9. The circuit of claim 1, wherein said plurality of bipolartransistors are NPN transistors.
 10. The circuit of claim 1, whereinsaid plurality of bipolar transistors comprises at least three bipolartransistors, and is connected to reduce the temperature-independentreference voltage by at least three times the base-emitter voltage dropof one of said bipolar transistors, to provide saidtemperature-dependent reference potential.
 11. The circuit of claim 1,wherein said plurality of bipolar transistors comprises exactly threebipolar transistors, and is connected to reduce thetemperature-independent reference voltage by exactly three times thebase-emitter voltage drop of one of said bipolar transistors, to providesaid temperature-dependent reference potential.
 12. A timing circuit,comprising:a capacitor; a first field-effect transistor, comprising agate, connected to discharge said capacitor; an additional stage,connected to said capacitor and configured to change state when saidcapacitor is discharged to a predetermined voltage; a bias voltagegenerating circuit, comprising multiple bipolar transistors and a secondfield-effect transistor, coupled to said gate of said first field-effecttransistor to provide a bias voltage which is equal to: the sum ofatemperature-independent reference voltage and the threshold voltage ofsaid second field-effect transistor, reduced by the combinedbase-emitter voltage drops of said multiple bipolar transistors.
 13. Thecircuit of claim 12, wherein said additional stage consists essentiallyof a comparator.
 14. The circuit of claim 12, wherein said gate of saidfirst field-effect transistor is connected to receive said bias voltagefrom a buffer amplifier having unity gain and low source impedance. 15.The circuit of claim 12, wherein said temperature-independent referencevoltage is derived from a bandgap voltage reference.
 16. The circuit ofclaim 12, further comprising a switching transistor connected to rapidlycharge said capacitor.
 17. An integrated circuit, comprising:at leastone timing circuit, comprising:a capacitor; a first field-effecttransistor, comprising a gate, connected to discharge said capacitor; aswitching transistor connected to rapidly charge said capacitor. anadditional stage, connected to said capacitor and configured to changestate when said capacitor is discharged to a predetermined voltage;wherein the gate of said first field-effect transistor is connected toreceive a bias voltage which is equal to: the sum ofatemperature-independent reference voltage and the threshold voltage ofsaid second field-effect transistor, reduced by the combinedbase-emitter voltage drops of said multiple bipolar transistors; saidtiming circuit being connected so that the leading edge of an incomingpulse will turn on said switching transistor, and the trailing edge ofthe incoming pulse will turn off said switching transistor; whereby saidtiming circuit will add a precisely predetermined delay onto thetrailing edge of each said pulse.
 18. The circuit of claim 17, whereinsaid additional stage consists essentially of a comparator.
 19. Thecircuit of claim 17, wherein said gate of said first field-effecttransistor is connected to receive said bias voltage from a bufferamplifier having unity gain and low source impedance.
 20. The circuit ofclaim 17, wherein said temperature-independent reference voltage isderived from a bandgap voltage reference.
 21. A timing circuit,comprising:a capacitor; a first field-effect transistor, comprising agate, connected to discharge said capacitor; a switching transistorconnected to rapidly charge said capacitor; a comparator, connected tosaid capacitor; a plurality of bipolar transistors, connected to reducea bandgap-derived reference voltage by a multiple of the base-emittervoltage drop of one of said plurality of bipolar transistors, to providea temperature-dependent reference potential; a plurality of firstcurrent sources, each of said second current sources being connected tokeep a respective one of said bipolar transistors operating in itsactive region; a second field-effect transistor, having source and drainterminals connected between a second current source and saidtemperature-dependent reference potential, and having a gate connectedto said drain terminal thereof; said gate of said first field effecttransistor being coupled to said gate of said second field-effecttransistor so that said gate of said first field-effect transistorreceives a voltage corresponding to the voltage on said gate of saidsecond field-effect transistor.